Many electronic devices perform their operations using timing of a clock signal (or multiple clock signals) generated by a clock generator included in the devices. Phase locked loop (PLL) clock generators are widely used to generate clock signals. A conventional PLL clock generator traditionally has a long frequency transition time when it switches from one frequency to the next during particular operations of the device. During such a frequency transition, the frequency behavior of the clock signal generated by the PLL clock generator is unpredictable. Thus, components in the device that use the clock signal for their operations may need to stop and wait until the PLL clock generator acquires the new frequency. This stop and wait action may hinder the performance of the device and waste device resources.